There is a known problem to synchronize a number of data flows when they are transmitted in parallel via a number of respective communication links/paths, being part of an interface or a bus. The problem is usually resolved by adding delays to align different data portions transmitted in parallel. However, the way it is usually performed in the prior art suffers from several drawbacks.
The task to be solved can be described with reference to FIG. 1 (prior art). An interface comprising a number of data paths/links conveys corresponding data flows from a transmitting side (TX) to a receiving side (RX). The receiving side (RX) of the interface (having more than one data path) should meet the following conditions in order to function properly:
1. Timing relationship between the sampling clock edge and the arriving data should meet conventional so-called setup and hold time requirements. In other words, the clock edge must be positioned within an arriving valid data portion (for example, within so-called data eye or eye pattern, in case of differential transmission) and not in a transition area between the valid data portions. The valid data, for example a valid data eye, can be understood as a time period during which one portion of digital information (for example, 1 or 0 of binary information) can be validly/stably detected by a corresponding detector at the receiver. Examples of valid data eyes are illustrated as white/light portions of FIG. 1. An open eye pattern corresponds to minimal signal distortion. Distortion of the signal waveform due to different types of interferences appears as closure of the eye pattern).2. For designs that are sensitive to binary word alignment, i.e. the data arriving to the receiver on each of the data lines has to be data that was originated on the same clock edge at the transmitting side.
FIG. 1 is an example of data arriving at the receiver side via four data paths. The first line shows clock pulses at the receiver (RX clk), the vertical lines show clock edges and a clock cycle there-between.
This example demonstrates possible conditions where data in each channel (CH-0 . . . CH-3) arrives at the receiver with a different delay and different amount of eye distortion: the channels arrive with dissimilar valid eye size. As seen in this example, for some paths/channels, the clock sampling (at clock edges demonstrated by vertical lines) is not within a valid data eye (shown by bright portions of transmission). For some paths, the delay is even higher than a clock cycle, with respect to the other paths.
FIG. 2 (prior art) illustrates a better situation, wherein the sampling clock edge is brought to the valid data area. It does meet the timing requirement (requirement 1), but the clock may capture data carried along different data paths at different clock cycles (for example, the clock samples on ch-0 data transmitted on time t3 while for ch-1 it samples data that was transmitted on time t2).
Naturally the question to be asked is what can be done to synchronize data eyes and align the data bits?
Typical solutions are:                Data-clock-alignment: Positioning the sampling edge of the clock at the center of the valid data (data eye) by adding delay to the data paths/channels; the Data-clock-alignment is usually combined with:        Word Alignment: Ensuring that the data is arriving at the right clock edge. Many prior art solutions are known, some of them by XILINX® (Xilinx FPGAs has IO (input/output) components called ISERDES and IDELAY, where the IDELAY may add delays to the received data path and the ISERDES may perform bitslip for word alignment).        
However, the problem remains that adding delay to data paths generally involves undesired jitter that, as a result, will narrow the valid portion of the data (such as data eye). This effect is more intrusive when higher data rates are required.
A number of solutions for data alignment have been developed by XILINX®. For example, XILINX proposed a design of 16 Channel, DDR LVDS Interface with real time windows monitoring. [Brandon Day, XAPP 860 (v.1.1) Jul. 17, 2008].
A so-called bit-align machine is designed to perform clock-data alignment on a data channel by dynamically varying the delay in the data path, until the optimal sampling point is found.
Xilinx FPGA characteristics derived from the document [Xilinx documentation: DS152 (v3.2) Apr. 1, 2011] provides us with a numeric example:
When looking at one channel of data, adding delay increment with a fixed amount of delay (˜78 ps delay), will narrow the eye by 10 ps. (The eye may be narrowed even by 18 ps, when HIGH_PERFORMANCE mode is set to FALSE). If twenty delay increments are required for a specific channel, it will narrow the valid data eye of this channel by 20×10=200 ps. This might be unacceptable for an interface where the arriving data has already quite a narrow eye.
Reducing the necessary delay to its minimum value would optimize the interface to handle tougher timing conditions. (In some cases, reducing the delay is crucial in order to meet timing requirements at all).
US2006188050A and U.S. Pat. No. 5,652,767A deal with similar problems. The first one proposes to line up all the plurality of data signals with the latest arriving data signal, while the second one is directed to reading the data with different phases of the clock.
It should be noted that, to the best of the inventor's knowledge, neither of the prior art references/products reduces the required Data-clock-alignment delays to the minimum value necessary to improve the conventional techniques mentioned hereinabove.